20 lines
923 B
Plaintext
20 lines
923 B
Plaintext
Verilog fuzzer to test the major Verilog compilers by generating random, valid
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and deterministic Verilog.
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It currently supports the following synthesis tools: Yosys, Xst, Vivado, Quartus
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and the following simulator: Icarus Verilog.
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The fuzzer generates combinational and behavioural Verilog to test the various
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tools. The most notable constructs that are supported and generated are the
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following:
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- module definitions with parameter definitions, inputs and outputs
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- module items, such as instantiations, continuous assignment, always blocks,
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initial blocks, parameter and local parameter declarations
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- most expressions, for example concatenation, arithmetic operations, ternary
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conditional operator
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- behavioural code in sequential always blocks
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- behavioural control flow such as if-else and for loops
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- declaration of wires and variables of any size, signed or unsigned
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- bit selection from wires and variables
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